1. Field of the Invention
The present invention relates to the field of integrated circuit packages, and more particularly, to surface mount packages having contacts arranged in a grid pattern (so called area array).
2. Description of the Related Art
Over the years, the electronics industry has minimized the size of integrated circuit chip designs. As integrated circuits become more dense and therefore smaller, the packaging of the integrated circuit becomes more complex. As a consequence, more and more input and output (I/O) connections become available for use with a single integrated circuit. For example, an integrated circuit with a size of 0.5 inches square can easily require 400 or more I/O connections.
The known packaging methods for low-cost standard integrated circuits having up to 300 I/O connections or so are not extendable to packages having more than 300 I/O connections. Presently, plastic quad flat packs (PQFPs) are the package type used for housing low cost high volume application specific integrated circuits (ASICs) having up to 300 I/O connections. The success achieved by PQFPs is attributable to their relative low-cost, which is based on high volume manufacturing that is achievable using conventional wire-bonding, leadframe and transfer molding technologies.
There are, however, a number of reasons why the PQFP packaging scheme is not suitable for packaging integrated circuits having more than 300 I/O connections. Namely, integrated circuits (e.g., ASICs) having more than 300 I/O connections typically produce a large amount of heat and utilize high frequency signal transmission. For example, an integrated circuit with 500 I/O connections might use 10 watts of power and operate at 100 MHz. However, QFPs cannot support frequencies in excess of 50 MHz because they lack a ground plane. Further, QFPs have difficultly in dissipating the heat produced by these highly integrated circuits due to their predominantly plastic body.
Another reason why PQFP packaging is not suitable for integrated circuits having more than 300 I/O connections is that the minimum pitch of outer leads of a leadframe is about 0.5 mm. These fine pitches cause problems with lead coplanarity and lead skew which result in a decrease in the surface mount assembly yield. A defect level in the 200 ppm (parts per million) range is not uncommon. In any event, as the number of I/O connections increases, finer pitches of the outer leads are required (i.e., below 0.5 mm) which accentuates these problems.
Still another reason is that as the number of I/O connections exceeds 300, the inner lead pitch needed drops below 8 mils. However, leadframe technology cannot provide an inner lead pitch below 8 mils. As a result, if QFPs are used, the package size would have to be increased so as to accommodate an enlarged leadframe. The enlarged leadframe would also require longer bonding wires to connect the chip pads to the inner leads. Even so, neither increasing package size nor increasing bonding wire length is acceptable to users.
However, a number of known integrated circuit packages, such as pin grid arrays, flip chip and TAB, are suitable for ICs having more than 300 I/O connections. The major problem of these packaging techniques is that they are a high end solution suitable for custom designs. That is, these packaging techniques typically cannot be implemented as standard, open-tooled, low-cost packages.
TAB refers to tape automated bonding which utilizes a continuous insulated tape which is similar to photographic film to produce a planer substrate for chips that are attached to individual sections, or frames, of the tape. A spider-like pattern of conductive traces is etched on each frame. An integrated circuit die is then carefully aligned over the center of the frame so that the contacts of the chip precisely match the conductive traces of the frame. The integrated circuit die can then be attached to the inner lead bonds of the TAB frame. Integrated circuits produced using the TAB technology can have conductive traces with a pitch of about 4 mils. These fine leads are attached to a printed circuit board (PCB) when the package is installed. Further, bumps are placed on the pads of the integrated circuit die. Alternatively, bumped TAB (BTAB) uses an interconnection method in which the bumps are not placed on the pads of the integrated circuit die, but on the thin copper foil.
Conventional TAB (i.e., one-metal TAB tape) has a problem in that it is unable to support high frequency signal transmission due to the lack of a ground plane. Although two-metal TAB tape is able to provide this feature, it is presently too expensive to be used in the packaging of standard integrated circuit parts. Furthermore, TAB tape has to be typically custom designed for each IC unlike leadframe technology.
Recent advances have produced demountable TAB (DTAB). DTAB is described in U.S. Pat. No. 5,162,975, entitled "Integrated Circuit Demountable TAB apparatus," which is commonly assigned with the subject application.
Flip chip is a technique in which a plurality of bumps in an area array arrangement on the integrated circuit die are mated with a matching pattern of pads on the substrate. The problem with flip chip is its high cost and lack of industry infrastructure and support. Pin grid arrays (PGAs) and land grid arrays (LGAs) are a family of customized multilayer ceramic or printed circuit package. The main drawback of PGAs and LGAs is that they typically require custom design and tooling specific to the integrated circuit and their costs fall above the QFP price curve ($0.10/pin vs. $0.02/pin). As a result, they are not a viable alternative for the QFP customer.
In sum, the known prior art fails to produce non-custom, low-cost surface mount packages which can facilitate over 300 I/O connections.